1. Field
The following description relates to a low-cost semiconductor device manufacturing method. The following description also relates to a semiconductor device that has a lowered manufacturing cost by reducing a masking process step used in a manufacturing process of the semiconductor device, and a manufacturing method of such a semiconductor.
2. Description of Related Art
Usually, a one-time manufacturing process of various semiconductor devices in one substrate imposes enormous expenses. These expenses arise because every time respective devices are produced, dozens of masks are inserted in the process flow. Accordingly, dozens of photolithography processes and etching processes accompany the masking steps. The more such processes of masking, photolithography, and masking are repeated, the more the manufacturing cost per unit increases. In order to produce significantly lower cost semiconductor devices or chips, it is helpful to minimize the number of masking steps. The process flow for manufacturing a Bipolar-Complementary Metal-Oxide-Semiconductor (CMOS)-Double-Diffused Metal-Oxide-Semiconductor (DMOS) (BCD) type technology that integrates many different active and passive devices on one substrate, for analog and power management applications is considered in greater detail.
The BCD consists of a combination of Bipolar, CMOS, and DMOS power devices, passive devices, and interconnection devices. An example of a device structure using integration in BCD technologies is a fully isolated Lateral n-channel Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) (nLDMOS). A BCD flow architecture using LDMOS devices, Bipolar, CMOS, one gate oxide, one polysilicon gate and three layers of metal, referred to as a whole as a 1P3M flow, with reference to the one layer of polysilicon gate and three layers of metal, may require more than 20 masking layers. For example, such an architecture typically uses 22-23 masking layers. The resulting wafer cost is therefore high, due to the use of so many masking layers and other related necessary processes.
In BCD, BiCMOS and CMOS technologies, to solve the increasing manufacturing cost challenge, the number of masking operations may be minimized. Here, BiCMOS is an advanced semiconductor technology that integrates the bipolar junction transistor and the CMOS transistor into a single integrated circuit device. If the manufacturing process is broken down into separate modules, most standard technologies use separate and dedicated N-channel low-doped-drain (NLDD) and P-channel low-doped-drain (PLDD) masking and implant operations to form the low-doped-drain (LDD) extensions of the N-channel and P-channel devices respectively. The NLDD mask is needed for formation of LDD (low doped drain) region for NMOS; the PLDD mask is necessarily needed for formation of LDD region for PMOS. Thus, if it is possible to reduce the number of such LDD masks used for formation of LDDs of NMOS and PMOS transistors, the manufacturing cost may be reduced.
Furthermore, it is desirable that the breakdown voltage (BVdss) of an nLDMOS is maximized, Resistance of Drain-Source in the On-state (Rdson) is minimized, and the manufacturing cost thereof is also minimized. Constructing a device that has these aspects is desirable because they improve performance and reliability of the device while keeping costs manageable. However, for example, in a BCD device such as power devices used in DC-DC or DC-AC high current converters, there is no known BCD process technology that satisfies all the requirements and goals just discussed.